The invention relates generally to thermal interface materials (TIMs) and more specifically to vertically aligned carbon nanotube (VACNT) array based TIMs.
Heat dissipation for high power density devices is a limiting factor impeding development of next generation higher performance electronic devices. FIG. 1 schematically illustrates prior art configuration of a thermal interface material (TIM) as used, for example, in a high power density device 10. One or more chips 20 are mounted on a packaging substrate 12 by means of solder balls 14. One of ordinary skill in the art would understand that there are a variety of methods for attaching chip 20 to packaging substrate 12. A TIM 16 is interposed between heat generating electronic devices such as chip 20 and heat sinks/exchangers 18 to facilitate heat conduction and maintain device 10 within a safe operating temperature range.
Thermal interface materials such as VACNT arrays and metal nanowire (MNW) arrays designed for handling these challenging heat loads are not meeting expectations. Junction temperatures of devices employing current TIMs are consequently expected to rise sharply causing degraded device performance, diminished service life and system reliability issues. Major factors behind the underperforming VACNT and MNW arrays include their limited areal density, transport engagement fraction and the actual contact area available for heat transport. VACNT array areal densities are generally in the 3-10% range with only a fraction (˜10-30%) of these within the TIM actually engaged in heat transfer. Even if VACNT arrays can eventually be grown to 2×-3× current areal densities, due to the cylindrically curved shape of a CNT only approximately 1% of their surface is estimated to be active in thermal transfer with the heat extraction surface.
Thus, a need exists for an improved thermal interface material having a higher density that provides greater heat transfer. There is also a need for a TIM having a larger contact area with adjoining surfaces.